Goal
Combine the receiver and transmitter blocks and verify the requirements with measurements.
Prerequisites: The first receiver after Parts 06–08, transmit and receive after Part 09, the full project after Parts 11–15. You do not need an FPGA.
Future lessons
- Requirements: modes, bandwidth, sample rates, levels, latency and quality metrics.
- Receive: samples → DDC → channel filter → demodulator → audio; a reasoned choice of where to put the AGC.
- Transmit: audio/telegraphy/data → modulator → interpolation and filtering → DUC → output samples.
- Channel: noise, interference, frequency and timing offsets, nonlinearity; the limits of the ADC/DAC models.
- Combining the floating-point, fixed-point and streaming models; measurements between blocks.
Lab plan
- Stage A: CW/AM receive. Stage B: SSB transmit through a channel model into the receiver; FM as an extra.
- Stage C: noise, interference, AGC and measurements. Stage D: integer and streaming versions.
- Write down the block interfaces: data type, I/Q or real signal, sample rate, bandwidth, scale, state and delay.
- Measure the unwanted sideband suppression, aliasing and spectral images, the SNR and the behavior during overload.
We do the experiments in Python with NumPy, SciPy and Matplotlib. We keep the parameters, units and plots. The base models use float64 and complex128; we add bit-depth limits in separate experiments.
Completion criteria
- I can run the full experiment again from the saved parameters and the random number generator seed.
- I can explain each block and I confirm the requirements with measurements.
- I set the modeled band explicitly: a tuning frequency written in MHz does not replace a valid sampling plan.
Result for the main project
The final transceiver model with configurations and a measurement report.