From Python to FPGA

Goal

Move verified blocks to a hardware description and compare them with the Python reference.

Prerequisites: Parts 14–15 and the verified blocks from Part 06. You can build project 17 before the FPGA part.

Future lessons

1. Clocking, registers, combinational logic, pipelines, latency and throughput.
2. Fixed-point arithmetic in HDL; DSP48 compute blocks and BRAM memory, the valid/ready protocol, reset and clock domain crossing.
3. The order of the move: NCO → mixer → FIR → CIC → DDC.
4. Test sequences, HDL simulation, delay compensation and bit-by-bit comparison.
5. An optional stage on the Arty A7; ADC/DAC and the radio frequency chain are connected after the models are verified.

Lab plan

• Export the input samples and the expected output from the Python integer model.
• Compare the HDL with the reference on an impulse, a tone, random data and limit levels.
• Add pauses in the stream and check the data transfer, the order of the samples and the reset.

We do the experiments in Python with NumPy, SciPy and Matplotlib. We keep the parameters, units and plots. The base models use float64 and complex128; we add bit-depth limits in separate experiments.

Completion criteria

• I can separate a difference in delay from a numerical error.
• I estimate the resources and the maximum clock frequency of the selected DDC; simulation does not need a board.

Result for the main project

A verified hardware DSP chain with test data from Python.